The present invention relates to on-chip magnetic devices, and more specifically, to on-chip magnetic structures and methods for minimizing magnetic losses for magnetic inductors.
On-chip magnetic inductor stacks are important passive elements with applications in the fields such as on-chip power converters and radio frequency (RF) integrated circuits. In order to achieve the high energy storage required for power management, on-chip inductors typically require relatively thick magnetic yoke materials (e.g., several microns or more).
Magnetic inductor stacks generally include alternating layers of magnetic material and dielectric material. The dielectric material helps prevent eddy current losses. The dielectric material used in the magnetic inductor stacks is generally deposited at low temperatures in order not to destroy the magnetic properties of the magnetic material. Low temperature oxides and nitrides have been used in the past but are prone to have pinholes, which can allow magnetic materials from adjacent layers to be electrically connected and unwanted eddy currents resulting in magnetic loss. The pinholes are particularly problematic for low temperature high throughput dielectric processes.